module mux_2_to_1(a, b, out,
		  outbar, sel);
	input a, b, sel;
	output out, outbar;
	reg out;
	
	always @ ( b or sel)
	begin
		case (sel)
			1'b1: out = a;
			1'b0: out = b;
		endcase
	end
	assign outbar = ~out;
endmodule

//hola

